Semiconductor integrated circuit

ABSTRACT

In a semiconductor integrated circuit including a phase comparator circuit for a PLL or DLL, overall lock precision of the PLL or DLL is improved by eliminating a dead zone of the phase comparator circuit and preventing output current offset of a charge pump circuit. The semiconductor integrated circuit includes a first circuit for activating a first phase difference signal corresponding to a phase difference between a first clock signal and a second clock signal when a phase of the first clock signal is delayed by more than a predetermined value in comparison with a phase of the second clock signal and activating a second phase difference signal corresponding to the phase difference when the phase of the first clock signal is advanced by more than a predetermined value in comparison with the phase of the second clock signal, a second circuit for activating a first pulse signal when an edge of the first clock signal is delayed in comparison with an edge of the second clock signal and activating a second pulse signal when the edge of the first clock signal is advanced in comparison with the edge of the second clock signal, a third circuit for combining the first phase difference signal and the first pulse signal, and a fourth circuit for combining the second phase difference signal and the second pulse signal.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor integratedcircuit including a phase comparator circuit for detecting phasedifference between two clock signals, and particularly to asemiconductor integrated circuit including a phase comparator circuitfor a PLL (phase locked loop) or DLL (delay locked loop).

BACKGROUND ART

[0002] For example, in a reproducing circuit for reproducing recordeddata or a receive circuit for receiving transmitted data, a PLL (phaselocked loop) having a combination of a voltage controlled oscillator anda phase comparator circuit or a DLL (delay locked loop) having acombination of a voltage controlled delay element and a phase comparatorcircuit is used to generate a clock signal synchronized to input data.

[0003] The structure of a PLL circuit using a conventional phasecomparator circuit is shown in FIG. 1. This PLL circuit comprises aphase comparator circuit 1 for comparing a phase of a reference clocksignal REF and a phase of a clock signal CLK to output an UP signal or aDOWN signal depending on the phase difference, a charge pump circuit 5for supplying output current I_(PDI) according to the UP signal and DOWNsignal output from the phase comparator circuit 1, a loop filter 6,having low pass characteristics, for converting output current I_(PDI)of the charge pump circuit 5 to a control voltage V_(CTL), and a VCO(voltage controlled oscillator) 7 oscillating at a frequency controlledby the control voltage V_(CTL) to output a clock signal CLK.

[0004] The structure of the phase comparator circuit as shown in FIG. 1is shown in FIG. 2. As shown in FIG. 2, the phase comparator circuit 1comprises two flip flop circuits 11 and 12 and an AND circuit 13.

[0005] A high level signal “1” is supplied to data input terminals D ofthe flip flop circuits 11 and 12. The flip flop circuit 11 outputs ahigh level UP signal synchronized with the rising edge of the referenceclock signal REF supplied to the clock input terminal CK, while the flipflop circuit 12 outputs a high level DOWN signal synchronized with therising edge of the clock signal CLK supplied to the clock input terminalCK.

[0006] The AND circuit 13 provides a high level signal to the clearterminals CLR of the flip flop circuits 11 and 12 when both the UPsignal and the DOWN signal become high levels. In this way, the flipflop circuits 11 and 12 are cleared and both the UP signal and the DOWNsignal become low levels.

[0007] As a result, in the case where the phase of the clock signal CLKis delayed compared to the reference clock signal REF, the phasecomparator circuit 1 outputs a high level UP signal from the rising edgeof the reference clock signal REF to the rising edge of the clock signalCLK. On the other hand, if the phase of the clock signal CLK is advancedcompared to the phase of the reference clock signal REF, the phasecomparator circuit 1 outputs a high level DOWN signal from the risingedge of the clock signal CLK to the rising edge of the reference clocksignal REF.

[0008] However, the minimum pulse width of the UP signal and the DOWNsignal that can be output by the phase comparator circuit 1 isdetermined by the manufacturing technology used, and in the case wherean absolute value of a phase difference between the clock signal CLK andthe reference clock signal REF is less than that minimum pulse width, adead zone exists where neither the UP signal or the DOWN signal areoutput. FIG. 3 shows a relationship between phase difference between thetwo clock signals and output current of the charge pump circuit when adead zone exists in the phase comparator circuit.

[0009] In order to eliminate the dead zone of the phase comparatorcircuit 1, it has been considered to increase the delay time of the ANDcircuit 13. If this is done, in the event that a phase differencebetween the clock signal CLK and the reference clock signal REF issmall, a pulse is output for both the UP signal and the DOWN signal andthe charge pump circuit 5 can supply output current I_(PDI) based on thewidth of these pulses. However, with respect to operation of the chargepump circuit 5, the following problems arise.

[0010] The structure of the charge pump circuit as shown in FIG. 1 isshown in FIG. 4. As shown in FIG. 4, the charge pump circuit 5 comprisesan inverter 51 for inverting the UP signal, a P-channel transistor Q1for supplying electrical current based on the inverted UP signal, anN-channel transistor Q2 for supplying electrical current based on theDOWN signal, and constant current sources 52 and 53. Here, the constantcurrent sources 52 and 53 normally stop operating as constant currentsources if a voltage greater than or equal to a specified voltage is notapplied. If the constant current sources 52 and 53 do not operate asconstant current sources, it is not possible to correctly balancecurrent in the transistors Q1 and Q2.

[0011] Specifically, in the case where the transistor Q1 operates closeto the power source voltage V_(DD), a voltage applied to the constantcurrent source 52 connected to transistor Q1 becomes small, andtherefore, current flowing when the transistor Q1 is on becomes smallerthan a steady value. Similarly, in the case where the transistor Q2operates close to the power source voltage V_(SS), a voltage applied tothe constant current source 53 connected to transistor Q2 becomes small,and therefore, current flowing when the transistor Q2 is on becomessmaller than a steady value. In this way, in the event that the constantcurrent sources 52 and 53 do not operate normally, then as shown in FIG.5, at a position where the phase difference between the clock signal CLKand the reference clock signal REF becomes zero, the output currentI_(PDI) of the charge pump circuit 5 no longer becomes zero.

[0012] As described above, in the case where a dead zone exists in thecharacteristics of the phase comparator circuit, or where the constantcurrent sources of the charge pump circuit do not operate normally evenif there is no dead zone in the characteristic of the phase comparatorcircuit, there are problems such as jitter of the clock signal CLKbecoming large and an offset arising in the phase of the clock signalCLK with respect to the reference clock signal REF.

DISCLOSURE OF THE INVENTION

[0013] In view of the above described situation, the object of thepresent invention is to improve overall lock precision of a PLL or DLLin a semiconductor integrated circuit including a phase comparatorcircuit for a PLL or DLL by preventing a dead zone of the phasecomparator circuit and preventing output current offset of a charge pumpcircuit.

[0014] In order to achieve the above described object, a semiconductorintegrated circuit according to the present invention comprises a firstcircuit for receiving a first clock signal and a second clock signal andfor activating a first phase difference signal corresponding to a phasedifference between the first clock signal and the second clock signalwhen a phase of the first clock signal is delayed by more than apredetermined value in comparison with a phase of the second clocksignal and activating a second phase difference signal corresponding tothe phase difference when the phase of the first clock signal isadvanced by more than a predetermined value in comparison with the phaseof the second clock signal, a second circuit for receiving the firstclock signal and the second clock signal and for activating a firstpulse signal when an edge of the first clock signal is delayed incomparison with an edge of the second clock signal and activating asecond pulse signal when the edge of the first clock signal is advancedin comparison with the edge of the second clock signal, a third circuitfor combining the first phase difference signal output from the firstcircuit and the first pulse signal output from the second circuit, and afourth circuit for combining the second phase difference signal outputfrom the first circuit and the second pulse signal output from thesecond circuit.

[0015] According to the present invention, by combining the firstcircuit having a dead zone with respect to detection of phase differencebetween the first clock signal and the second clock signal and thesecond circuit for determining whether the second clock signal edge isahead of or behind the first clock signal edge, it is possible to getrid of the dead zone of the phase comparator circuit and to preventoutput current offset of the charge pump circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Advantages and features of the present invention will becomeclear from reference to the following detailed description and drawings.In these drawings, the same reference numerals represent the samestructural elements.

[0017]FIG. 1 is a block diagram showing the structure of a PLL circuitusing a conventional phase comparator circuit.

[0018]FIG. 2 is a circuit diagram showing the structure of the phasecomparator circuit shown in FIG. 1

[0019]FIG. 3 is a drawing showing a relationship between phasedifference of two clock signals and output current of a charge pumpcircuit when a dead zone exists in the phase comparator circuit.

[0020]FIG. 4 is a circuit diagram showing the structure of a charge pumpcircuit shown in FIG. 1.

[0021]FIG. 5 is a drawing showing a relationship between phasedifference of two clock signals and output current of a charge pumpcircuit when a constant current source is not operating normally.

[0022]FIG. 6 is a block diagram of a PLL circuit using a phasecomparator circuit included in a semiconductor integrated circuitaccording to a first embodiment of the present invention.

[0023]FIG. 7 is a circuit diagram showing the structure of anarbitration circuit shown in FIG. 6.

[0024]FIGS. 8A and 8B are timing charts showing waveforms of inputsignals of the arbitration circuit shown in FIG. 7.

[0025]FIG. 9 is a drawing showing a relationship between phasedifference of two clock signals and output current of the charge pumpcircuit when using the arbitration circuit shown in FIG. 7.

[0026] FIGS. 10A-10D are timing charts showing waveforms of respectivesignals in the phase comparator circuit shown in FIG. 6.

[0027]FIG. 11 is a drawing showing a relationship between phasedifference of two clock signals and output current of the charge pumpcircuit when using the PLL circuit shown in FIG. 6.

[0028]FIG. 12 is a block diagram of a DLL circuit using a phasecomparator circuit included in a semiconductor integrated circuitaccording to a second embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0029]FIG. 6 is a block diagram of a PLL circuit using a phasecomparator circuit included in a semiconductor integrated circuitaccording to a first embodiment of the present invention.

[0030] As shown in FIG. 6, this PLL circuit comprises a phase comparatorcircuit 10 for comparing a phase of a reference clock signal REF and aphase of a clock signal CLK to output an UP signal and a DOWN signaldepending on the phase difference, a charge pump circuit 5 for supplyingoutput current I_(PDI) according to the UP signal and DOWN signal outputfrom the phase comparator circuit 10, a loop filter 6, having a low passcharacteristic, for converting output current I_(PDI) supplied from thecharge pump circuit 5 to a control voltage V_(CTL), and a VCO (voltagecontrolled oscillator) 7 for oscillating at a frequency controlled bythe control voltage V_(CTL) to output the clock signal CLK.

[0031] Here, the phase comparator circuit 10 comprises a phasecomparator circuit 1 for comparing the phase of the reference clocksignal REF with the phase of the clock signal CLK to output phasedifference signals UP0 and DOWN0 depending on the phase difference, anarbitration circuit 2 for outputting a pulse signal UP1 when a risingedge of the clock signal CLK is delayed compared to a rising edge of thereference clock signal REF and outputting a pulse signal DOWN1 when therising edge of the clock signal CLK is advanced compared to the risingedge of the reference clock signal REF, a combining circuit 3 forcombining and outputting the phase difference signal UP0 and the pulsesignal UP1, and a combining circuit 4 for combining and outputting thephase difference signal DOWN0 and the pulse signal DOWN1.

[0032] The phase comparator circuit 1 is the same as that shown in FIG.2. If the phase of the clock signal CLK is delayed compared to the phaseof the reference clock signal REF, the phase comparator circuit 1outputs a high level UP signal from the rising edge of the referenceclock signal REF until the rising edge of the clock signal CLK. On theother hand, if the phase of the clock signal CLK is advanced compared tothe phase of the reference clock signal REF, the phase comparatorcircuit 1 outputs a high level DOWN signal from the rising edge of theclock signal CLK until the rising edge of the reference clock signalREF.

[0033] In the phase comparator circuit 1, in the event that an absolutevalue of a phase difference between the clock signal CLK and thereference clock signal REF is less than or equal to the minimum pulsewidth that can be determined by the manufacturing technology, there is adead zone where neither the UP signal or the DOWN signal are output(refer to FIG. 3). However, if the phase difference between the clocksignal CLK and the reference clock signal REF is zero, since neither theUP signal or the DOWN signal are output, output current I_(PDI) of thecharge pump circuit 5 becomes zero and no offset occurs. The structureof the charge pump circuit 5 is the same as that shown in FIG. 4.

[0034] The structure of the arbitration circuit as shown in FIG. 6 isshown in FIG. 7. As shown in FIG. 7, the arbitration circuit 2 comprisesan edge detection circuit 8 and a pulse generating circuit 9. The edgedetection circuit 8 comprises NAND circuits 81 and 82, a first invertermade up of a P-channel transistor Q3 and an N-channel transistor Q4, anda second inverter made up of a P-channel transistor Q5 and an N-channeltransistor Q6. Also, the pulse generating circuit 9 comprises inverters91-96 and AND circuits 97 and 98.

[0035] A description will be given for the case where a rising edge ofthe reference clock signal REF is advanced compared to the rising edgeof the clock signal CLK, as shown in FIG. 8A. If the reference clocksignal REF becomes high level, output of the NAND circuit 81 becomes lowlevel. Next, at the point in time where the clock signal CLK becomes ahigh level, the output of the first inverter becomes a high level. Onthe other hand, the output of the NAND circuit 81 is maintained at ahigh level. In this way, in the pulse generating circuit 9, a pulsesignal UP1 having a pulse width corresponding to delay time of theinverters 91 to 93 is output from the AND circuit 97.

[0036] A description will be given for the case where a rising edge ofthe clock signal CLK is advanced compared to the rising edge of thereference clock signal REF, as shown in FIG. 8B. If the clock signal CLKbecomes a high level, output of the NAND circuit 82 becomes a low level.Next, at the point in time where the reference clock signal REF becomesa high level, the output of the second inverter becomes a high level. Onthe other hand, the output of the NAND circuit 82 is maintained at ahigh level. In this way, in the pulse generating circuit 9, a pulsesignal DOWN1 having a pulse width corresponding to delay time of theinverters 94-96 is output from the AND circuit 98.

[0037]FIG. 9 shows a relationship between phase difference of two clocksignals and output current of the charge pump circuit when using thearbitration circuit shown in FIG. 7. The arbitration circuit shown inFIG. 7 outputs a pulse signal having a fixed pulse width only inresponse to the order of the reference clock signal REF and the clocksignal CLK. Accordingly, if this pulse signal is input to a charge pumpcircuit, the charge pump circuit outputs a positive constant currentwhen the phase difference between the clock signal CLK and the,reference clock signal REF is negative, and outputs a negative constantcurrent when the phase difference is positive.

[0038] Referring again to FIG. 6, in the phase comparator circuit 10,the phase difference signals UP0 and DOWN0 output from the phasecomparator circuit 1 are respectively combined with the pulse signalsUP1 and DOWN 1 output from the arbitration circuit 2 by the combiningcircuits 3 and 4, to generate the UP signal and the DOWN signal. It ispossible to use, for example, OR circuits as the combining circuits 3and 4.

[0039] Waveforms of respective signals of the phase comparator circuit10 shown in FIG. 6 are shown in FIGS. 10A-10D.

[0040]FIGS. 10A and 10B show waveforms of respective signals in the casewhere the phase of the reference clock signal REF is advanced comparedto the phase of the clock signal CLK. In FIG. 10A, an absolute value Δ tof phase difference is large and a period for which the UP signal is ahigh level is determined by the phase difference signal UP0. In FIG.10B, an absolute value Δ t of phase difference is small and a period forwhich the UP signal is a high level is determined by the pulse signalUP1.

[0041]FIGS. 10C and 10D show waveforms of respective signals in the casewhere the phase of the clock signal CLK is advanced compared to thephase of the reference clock signal REF. In FIG. 10C, an absolute valueΔ t of phase difference is small and a period for which the DOWN signalis a high level is determined by the pulse signal DOWN 1. In FIG. 10D,an absolute value Δ t of phase difference is large and a period forwhich the DOWN signal is a high level is determined by the phasedifference signal DOWN0.

[0042] By driving the charge pump circuit 5 using the UP signal and DOWNsignal generated in this way, a relationship between phase difference ofthe two clock signals and output current of the charge pump circuitbecomes a characteristic that is an addition of the characteristic shownin FIG. 3 and the characteristic shown in FIG. 9. FIG. 11 shows arelationship between the phase difference of the two clock signals andoutput current of the charge pump circuit for the PLL circuit shown inFIG. 6. Outside the dead zone of the phase comparator circuit 1, outputcurrent of the charge pump circuit varies in response to phasedifference between the two clock signals, while inside the dead zone,polarity of the output current of the charge pump circuit is varieddepending on whether the phase difference is positive or negative, owingto the characteristic of the arbitration circuit 2.

[0043] In this embodiment, by driving the charge pump circuit 5 usingthe phase comparator circuit 10, there is no dead zone where the outputcurrent of the charge pump circuit 5 becomes zero, no offset occurs inoutput current when the phase of the clock signal CLK and the phase ofthe reference clock signal REF are coincident. Accordingly, byconverting output current I_(PDI) supplied from the charge pump circuit5 into a control voltage V_(CTL) using the loop filter 6 and controllingthe VCO 7 using this control voltage V_(CTL), it is possible to realizea PLL that reduces jitter due to a dead zone of the phase comparatorcircuit and also a phase offset between the clock signal CLK and thereference clock signal REF.

[0044] Next, a second embodiment of the present invention will bedescribed.

[0045]FIG. 12 is a block diagram of a DLL circuit using a phasecomparator circuit contained in a semiconductor integrated circuitaccording to the second embodiment of the present invention. In this DLLcircuit, a VCO 7 shown in FIG. 6 is replaced with a variable delaycircuit 20.

[0046] This variable delay circuit 20 receives a reference clock REF asan input, delays the reference clock REF by a delay period that iscontrolled by a control voltage V_(CTL) output from a loop filter 6, andoutputs the delayed reference clock REF as a clock signal CLK. Thevariable delay circuit 20 can also be made up of a plurality of delayelements having a delay period controlled by a control voltage. In thiscase, it is possible to output a number of multiphase clock signals fromthese delay elements. The multiphase clock signals are used to decodehigh-speed serial-transmission data, for example.

[0047] In this embodiment, by driving the charge pump circuit 5 usingthe phase comparator circuit 10, there is no dead zone where the outputcurrent of the charge pump circuit 5 becomes zero, no offset occurs inoutput current when the phase of the clock signal CLK and the phase ofthe reference clock signal REF are coincident. Accordingly, byconverting output current I_(PDI) supplied from the charge pump circuit5 into a control voltage V_(CTL) using the loop filter 6 and controllingthe variable delay circuit 20 using this control voltage V_(CTL), it ispossible to realize a DLL that reduces jitter due to a dead zone of thephase comparator circuit and also a phase offset between the clocksignal CLK and the reference clock signal REF.

[0048] As has been described above, according to the present invention,in a semiconductor integrated circuit including a phase comparatorcircuit using a PLL or a DLL, it is possible to eliminate a dead zone ofthe comparator circuit and also to prevent offset of a charge pumpcircuit output current. In this way, it is possible to reduce jitter andoffset of a clock signal, and to improve overall lock precision of a PLLor DLL.

[0049] The present invention has been described based on embodiments,but the present invention is not limited to the above describedembodiments and various forms and modifications are possible within therange of the attached patent claims.

INDUSTRIAL APPLICABILITY

[0050] The present inventions can be used in a PLL or DLL for generatinga clock signal synchronized with input data.

1. A semiconductor integrated circuit, comprising: a first circuit for receiving a first clock signal and a second clock signal and for activating a first phase difference signal corresponding to a phase difference between the first clock signal and the second clock signal when a phase of the first clock signal is delayed by more than a predetermined value in comparison with a phase of the second clock signal and activating a second phase difference signal corresponding to the phase difference when the phase of the first clock signal is advanced by more than a predetermined value in comparison with the phase of the second clock signal; a second circuit for receiving the first clock signal and the second clock signal and for activating a first pulse signal when an edge of the first clock signal is delayed in comparison with an edge of the second clock signal and activating a second pulse signal when the edge of the first clock signal is advanced in comparison with the edge of the second clock signal; a third circuit for combining the first phase difference signal output from said first circuit and the first pulse signal output from said second circuit; and a fourth circuit for combining the second phase difference signal output from said first circuit and the second pulse signal output from said second circuit.
 2. A semiconductor integrated circuit according to claim 1, wherein said second circuit activates the first pulse signal for a fixed period regardless of the phase difference between the first clock signal and the second clock signal in the case where the edge of the first clock signal is delayed in comparison with the edge of the second clock signal and activates the second pulse signal for a fixed period regardless of the phase difference in the case where the edge of the first clock signal is advanced in comparison with the edge of the second clock signal.
 3. A semiconductor integrated circuit according to claim 1, wherein said third circuit includes an OR circuit for subjecting the first phase difference signal output from said first circuit and the first pulse signal output from said second circuit to a logical OR operation, and said fourth circuit includes an OR circuit for subjecting the second phase difference signal output from said first circuit and the second pulse signal output from said second circuit to a logical OR operation. 